There are known many technologies for forming a source line of a semiconductor memory device, and of these, a self-aligned source process is widely used. During the self-aligned source process, after a stack gate structure is formed, a cell region excluding a common source portion is covered with a photosensitive film, a device separation film at a source line portion is removed by etching, and ion implantation is performed to form a common source line.
Example FIG. 1A illustrates a layout view of a semiconductor memory cell array. Example FIG. 1B illustrates a pattern diagram of an active region in a semiconductor memory cell array. Example FIGS. 2A to 2D illustrate a method of manufacturing a semiconductor memory device taken along the line II-II of example FIG. 1A. Example FIGS. 3A to 3D illustrate a method of manufacturing a semiconductor memory device taken along the line III-III of example FIG. 1A.
As illustrated in example FIGS. 1A, 1B, 2A, and 3A, device separation film 12 may be formed in a device separation region of semiconductor substrate 11. Here, as an active region mask pattern for separating the device separation region from the active region, a linear mask pattern illustrated in example FIG. 1B by which a linear active region and a linear device separation region are formed may be used. Tunnel oxide film 13 and first polysilicon film 14 may then be sequentially formed on and/or over the entire structure and then patterned by a lithography process and an etching process with a floating gate mask, thereby forming a floating gate. Dielectric film 15, second polysilicon film 16, tungsten silicide film 17 and oxide film 18 may then be sequentially formed on and/or over the entire structure and then patterned by a lithography process and an etching process with a control gate mask, thereby forming a control gate. In this way, stack gate structure 20 in which a floating gate and a control gate are laminated is formed. Photosensitive film 19 may then be formed on and/or over the entire structure and then patterned by an exposure process and a development process with a self-aligned source mask, such that a source line portion is exposed.
As illustrated in example FIGS. 1A, 2B, and 3B, a self-aligned source (SAS) etching process may be performed to remove exposed device separation film 12 at the source line portion, such that semiconductor substrate 11 at the source line portion is exposed. After the self-aligned source etching process is completed, a curing process may be performed.
A cell source ion implantation process may be performed with patterned photosensitive film 19 as an ion implantation mask. Then, impurity ions may be implanted into semiconductor substrate 11 at the source line portion, thereby forming a common source line 21, 23.
When device separation film 12 is removed, a residue may remain. Even if ions are implanted during a subsequent process, common source line 21, 23 may not be satisfactorily formed. In addition, as illustrated in example FIG. 3B, since the profiles of common source lines 21, 23 have a step between the active region and the device separation region, they may be formed in a bent shape.
As illustrated in example FIGS. 1A, 2C, and 3C, the entire cell array may be exposed and an impurity ion implantation process performed, thereby forming drain region 22.
As illustrated in example FIGS. 1A, 2D, and 3D, an insulating film may be formed on and/or over the entire structure and an entire surface etching process is performed, thereby forming spacers 24 at the sidewalls of stack gate structure 20.
In accordance with the aforementioned structure, since multiple cells are connected to a single source line, i.e., the common source line is used, source resistance is large, and as a result, a cell current characteristic may be deteriorated. In particular, since the active region mask pattern for separation the device separation region from the active region, the linear pattern illustrated in example FIG. 1B by which a linear active region and a linear device separation region are formed is used, the device separation film is formed on the common source line. Accordingly, a residue may remain when the device separation film is removed so as to form the common source line. As a result, the common source line may not be satisfactorily formed. For this reason, source resistance may be further increased and at worst, the common source line may not be satisfactorily functioned.